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This post was updated on May 18, 2016; 2:54am.
Hi all,
I applied the two hotfixes and the 8.3 fw_upgrade script and rebooted my shield and it never came back up again. (Big mistake).
I now get this via the console:
OCTBOOT2BIN not found
Error: Trying embedded failsafe...
I'm assuming this is a stage 2 bootloader issue and I need to tftp a file?
I'm competent with Linux and tftp/console so won't be too difficult to help 
Full output attached:
output.txt
Full output:
OCTBOOT2BIN not found
Error: Trying embedded failsafe...
g 7 (0xc00756bc)
Calling 8: 0xc002b58c
board_init_f: Boot flag: 0x2
board_init_f: Done calling 8 (0xc00756c0)
Calling 9: 0xc002f934
board_init_f: Boot flag: 0x2
board_init_f: Done calling 9 (0xc00756c4)
Calling 10: 0xc0053920
board_init_f: Boot flag: 0x2
Board TLV descriptor Read - RHino continues ... 2 board 0x40 major 1 minor 0, DDR HERTZ 0 hz
Rhino: early board init, mem_clk 0x29b ..
board_init_f: Done calling 10 (0xc00756c8)
Calling 11: 0xc0025978
board_init_f: Boot flag: 0x2
board_init_f: Done calling 11 (0xc00756cc)
Calling 12: 0xc0024cf0
board_init_f: Boot flag: 0x2
board_init_f: Done calling 12 (0xc00756d0)
Calling 13: 0xc002b32c
board_init_f: Boot flag: 0x2
board_init_f: Done calling 13 (0xc00756d4)
Calling 14: 0xc00473b8
board_init_f: Done calling 14 (0xc00756d8)
Calling 15: 0xc0037d90
board_init_f: Boot flag: 0x2
board_init_f: Done calling 15 (0xc00756dc)
Calling 16: 0xc002b2b0
board_init_f: Boot flag: 0x2
U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: Dec 01 2014 - 16:34:53)
board_init_f: Done calling 16 (0xc00756e0)
Calling 17: 0xc0022204
board_init_f: Boot flag: 0x2
board_init_f: Done calling 17 (0xc00756e4)
Calling 18: 0xc00237b8
board_init_f: Boot flag: 0x2
Initializing DRAM
U-Boot is not RAM-resident
Found DDR configuration for SFF7000
Rhino: cpu_id 0xd9602 board_type 0x40 major 0x1 minor 0x0 mask 1 ...
Initializing DDR, clock = 667000000hz, reference = 50000000hz
LMC0_DCLK_CNT: 0xffffffffffffffff
Cavium Inc. OCTEON SDK version 3.1.0_p4, build 534: $Revision: 101360 $
EARLY FILL COUNT : 13, cpu_hertz:1000000000, ddr_hertz:667000000
LMC0 Asserting DDR_RESET_L
DDR Reference Hertz = 50000000
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334
clkr: 0, en[2]: 3, clkf: 39, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 1, en[2]: 3, clkf: 79, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 2, en[2]: 3, clkf: 119, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334
clkr: 2, en[1]: 2, clkf: 79, pll_MHz: 1333, ddr_hertz: 666666666, error: 333334
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334 <==
LMC0 De-asserting DDR_RESET_L
▒▒j
CONTROL_CTL : 4
MIN_CAS_LATENCY : 0
OFFSET_EN : 1
OFFSET_UDIMM : 2
OFFSET_RDIMM : 2
DDR_RTT_NOM_AUTO : 0
DDR_RODT_CTL_AUTO : 0
RLEVEL_COMP_OFFSET : 7
RLEVEL_COMPUTE : 0
DDR2T_UDIMM : 1
DDR2T_RDIMM : 1
FPRCH2 : 2
-------------------------------------------------
Desired CAS Latency : 10
CAS Latencies supported in DIMM : 5 6 7 8 9 10 11
CAS Latency : 10
DDR Clock Rate (tCLK) : 1500 ps
Core Clock Rate (eCLK) : 1000 ps
Medium Timebase (MTB) : 125 ps
Minimum Cycle Time (tCKmin) : 1250 ps
Minimum CAS Latency Time (tAAmin) : 13750 ps
Write Recovery Time (tWR) : 15000 ps
Minimum RAS to CAS delay (tRCD) : 13750 ps
Minimum Row Active to Row Active delay (tRRD) : 6000 ps
Minimum Row Precharge Delay (tRP) : 13750 ps
Minimum Active to Precharge (tRAS) : 35000 ps
Minimum Active to Active/Refresh Delay (tRC) : 48750 ps
Minimum Refresh Recovery Delay (tRFC) : 260000 ps
Internal write to read command delay (tWTR) : 7500 ps
Min Internal Rd to Precharge Cmd Delay (tRTP) : 7500 ps
Minimum Four Activate Window Delay (tFAW) : 30000 ps
LMC_SCRAMBLE_CFG0 : 0x0000000000000000
LMC_SCRAMBLE_CFG1 : 0x0000000000000000
LMC_CONFIG : 0x1008090a2c290044
LMC_CONTROL : 0x000007801f038024
TIMING_PARAMS0 : 0x000065112ccc3400
TIMING_PARAMS1 : 0x0000f2bd34592970
CAS Write Latency : 7
Write recovery for auto precharge (WRP) : 5
MODEREG_PARAMS0 : 0x0000000000a30002
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0
DIC 40, 40, 40, 40 ohms : 0,0,0,0
MODEREG_PARAMS1 : 0x0000000000000600
LMC_NXM : 0x000000000000040e
WODT_MASK : 0x0000000000000001
RODT_MASK : 0x0000000000000000
DYN_RTT_NOM_MASK : 0x00
PHY_CTL : 0x0000001200000000
PHY_CTL : 0x0000001200200000
Performing Write-Leveling
MODE32B : 1
Rank(0) Wlevel Debug Results : 00000 00000 00000 00000 00000 0001e 0001f 000f0 000f8
Rank(0) Wlevel Rank 0x3, 0x0000600000000082 : 0 0 0 0 0 0 0 4 2
MODE32B : 1
Waiting 159448 usecs for ZQCS calibrations to start
▒B▒▒Jj
rlevel_scoreboard[rtt_nom=2][rodt_ctl=3][rankx=0].score:30
Read ODT_CTL : 0x2 (30 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 000ff 000ff 000ff 001f0
Rank(0) Rlevel Rank 0x3, 0x00C6186186145146 : 6 6 6 6 6 5 5 5 6 (30)
rlevel_scoreboard[rtt_nom=2][rodt_ctl=2][rankx=0].score:30
Read ODT_CTL : 0x1 (20 ohms)
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 000ff 000fe 000ff 001f0
Rank(0) Rlevel Rank 0x3, 0x00C6186186145146 : 6 6 6 6 6 5 5 5 6 (25)
rlevel_scoreboard[rtt_nom=2][rodt_ctl=1][rankx=0].score:25
DDR__PTUNE/DDR__NTUNE : 9/7
Evaluating Read-Leveling Scoreboard.
rlevel_scoreboard[rtt_nom=2][rodt_ctl=5][rankx=0].score:77
rodt_score:77, best_rodt_score:9999999
rlevel_scoreboard[rtt_nom=2][rodt_ctl=4][rankx=0].score:30
rodt_score:30, best_rodt_score:77
rlevel_scoreboard[rtt_nom=2][rodt_ctl=3][rankx=0].score:30
rodt_score:30, best_rodt_score:30
rlevel_scoreboard[rtt_nom=2][rodt_ctl=2][rankx=0].score:30
rodt_score:30, best_rodt_score:30
rlevel_scoreboard[rtt_nom=2][rodt_ctl=1][rankx=0].score:25
rodt_score:25, best_rodt_score:30
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0
DIC 40, 40, 40, 40 ohms : 0,0,0,0
Read ODT_CTL : 0x3 (40 ohms)
Rank(0) Rlevel Rank 0x1, 0x0046186186145146 : 6 6 6 6 6 5 5 5 6 (25)
DDR2T : 1
Performing software Write-Leveling
Rank Address: 0x0
Testing byte 0 delay 2
1: [0x8000000004000000] 0x00000000000000BF expected 0x00000000000000FF xor 0000000000000040
byte 0 delay 2 Errors
Testing byte 0 delay 10
byte 0(0x0) delay 10 Passed
Testing byte 1 delay 4
1: [0x8000000004000000] 0x000000000000BF00 expected 0x000000000000FF00 xor 0000000000004000
byte 1 delay 4 Errors
Testing byte 1 delay 12
byte 1(0x0) delay 12 Passed
Testing byte 2 delay 0
1: [0x8000000004000000] 0x0000000000BF0000 expected 0x0000000000FF0000 xor 0000000000400000
byte 2 delay 0 Errors
Testing byte 2 delay 8
byte 2(0x0) delay 8 Passed
Testing byte 3 delay 0
1: [0x8000000004000000] 0x00000000BF000000 expected 0x00000000FF000000 xor 0000000040000000
byte 3 delay 0 Errors
Testing byte 3 delay 8
byte 3(0x0) delay 8 Passed
Rank(0) Wlevel Rank 0x1, 0x0000200000A4218A : 0(e) 0(e) 0(e) 0(e) 10(e) 8 8 12 10
LMC0 Configuration Completed: 1024 MB
Measured DDR clock 666666478 Hz
Mem size in MBYTES: 1024
RHino: new Ram size 1024MiB (0x40000000)
Ram size 1024MiB (0x40000000)
Clearing memory from 0 to 1048576
Done clearing memory
board_init_f: Done calling 18 (0xc00756e8)
Calling 19: 0xc002b2f0
board_init_f: Boot flag: 0x2
Empty memory test
board_init_f: Done calling 19 (0xc00756ec)
Calling 20: 0xc0025a18
board_init_f: Boot flag: 0x2
board_init_f: Done calling 20 (0xc00756f0)
Calling 21: 0xc0053918
board_init_f: Boot flag: 0x2
board_init_f: Done calling 21 (0xc00756f4)
Calling 22: 0xc002ed50
board_init_f: Boot flag: 0x2
SFF7000 board revision major:1, minor:0, serial #:
OCTEON CN7020-AAP pass 1.2, Core clock: 1000 MHz, IO clock: 600 MHz, DDR clock: 667 MHz (1334 Mhz DDR)
Rhino: End of display banner ...
board_init_f: Done calling 22 (0xc00756f8)
board_init_f: Done calling init sequence
flushing L2 cache...
Invalidating icache
Done.
Unlocking U-Boot from cache...
x10000000
Adjusted memory top is 0x40000000
Setting load address to 0x20000000, size 0x10000000
Reserving 0xf000000 bytes of memory at 0x100000 for the Linux kernel
bootmem descriptor address (looked up): 0x6c108
Setting up U-Boot prompt for board type 64.
prompt environment variable not set.
Setting prompt to Octeon sff7000#
Reading eeprom...
Performing OCTEON FDT fixups
Packing flat device tree
Setting numcores to 2
ethaddr not found in environment
Setting IP address...
Done.
Reserving first 1MB of memory
Initializing stdio...
Initializing jump table...
Initializing console...
Console initialized
Setting stdin, stdout and stderr to serial port
Setting load address...
Configuring misc...
MMC:
Octeon sff7000#
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Locked
May 16, 2016; 11:44pm
