Posted by Grommish on May 01, 2020; 11:17pm
URL: https://itus.accessinnov.com/FIRMWARE-Itus-Networks-Shield-Firmware-Upgrade-WIP-tp1726p1981.html

Ok, so, I need someone with C/C++ experience to give me a handle.. Something broke in the source and MIPS64 is of no concern to them.

drivers/net/ethernet/cavium/octeon/octeon3-core.c: In function 'octeon3_eth_probe':
drivers/net/ethernet/cavium/octeon/octeon3-core.c:1938:27: error: assignment to 'int (*)(struct ptp_clock_info *, struct timespec64 *)' from incompatible pointer type 'int (*)(struct ptp_clock_info *, struct timespec *)' [-Werror=incompatible-pointer-types]
  priv->ptp_info.gettime64 = octeon3_gettime;
                           ^
drivers/net/ethernet/cavium/octeon/octeon3-core.c:1939:27: error: assignment to 'int (*)(struct ptp_clock_info *, const struct timespec64 *)' from incompatible pointer type 'int (*)(struct ptp_clock_info *, const struct timespec *)' [-Werror=incompatible-pointer-types]
  priv->ptp_info.settime64 = octeon3_settime;
                           ^
cc1: some warnings being treated as errors
make[10]: *** [scripts/Makefile.build:304: drivers/net/ethernet/cavium/octeon/octeon3-core.o] Error 1


Here are the structs.

static int octeon3_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
        struct octeon3_ethernet *priv;
        u64                     ns;
        u32                     remainder;
        unsigned long           flags;

        priv = container_of(ptp, struct octeon3_ethernet, ptp_info);

        spin_lock_irqsave(&priv->ptp_lock, flags);
        ns = timecounter_read(&priv->tc);
        spin_unlock_irqrestore(&priv->ptp_lock, flags);
        ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
        ts->tv_nsec = remainder;

        return 0;
}

static int octeon3_settime(struct ptp_clock_info *ptp,
                           const struct timespec *ts)
{
        struct octeon3_ethernet *priv;
        u64                     ns;
        unsigned long           flags;

        priv = container_of(ptp, struct octeon3_ethernet, ptp_info);
        ns = timespec_to_ns(ts);

        spin_lock_irqsave(&priv->ptp_lock, flags);
        timecounter_init(&priv->tc, &priv->cc, ns);
        spin_unlock_irqrestore(&priv->ptp_lock, flags);

        return 0;
}



From the patch lore:

>
> [snip]
>
>> +/* Registers are accessed via xkphys */
>> +#define SSO_BASE 0x1670000000000ull
>> +#define SSO_ADDR(node) (SET_XKPHYS + NODE_OFFSET(node) +      \
>> + SSO_BASE)
>> +#define GRP_OFFSET(grp) ((grp) << 16)
>> +#define GRP_ADDR(n, g) (SSO_ADDR(n) + GRP_OFFSET(g))
>> +#define SSO_GRP_AQ_CNT(n, g) (GRP_ADDR(n, g)   + 0x20000700)
>> +
>> +#define MIO_PTP_BASE 0x1070000000000ull
>> +#define MIO_PTP_ADDR(node) (SET_XKPHYS + NODE_OFFSET(node) +      \
>> + MIO_PTP_BASE)
>> +#define MIO_PTP_CLOCK_CFG(node) (MIO_PTP_ADDR(node) + 0xf00)
>> +#define MIO_PTP_CLOCK_HI(node) (MIO_PTP_ADDR(node) + 0xf10)
>> +#define MIO_PTP_CLOCK_COMP(node) (MIO_PTP_ADDR(node) + 0xf18)
>
> I am sure this will work great on anything but MIPS64 ;)

Sarcasm duly noted.

That said, by definition it is exactly an OCTEON-III/MIPS64, and can
never be anything else.  It is known a priori that the hardware and this
driver will never be used anywhere else.