Posted by Roadrunnere42 on Feb 22, 2016; 9:29pm
URL: https://itus.accessinnov.com/How-do-I-completely-reset-tp131p150.html

Right here a quick low-down on what i have found about the shield booting

when you power on the Shield it loads

OCTEON eMMC stage 1 bootloader

this then give control over to

OCTBOOT2BIN

which is stage 2  the build time  that my two Shields display are  build time Mar 2015 and both are on 1.51 sp1

U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: Mar 27 2015 - 10:49:38)

All the trouble people seem to have are with builds dates 2014, i think this could either be firmware version RC1 or the beta firmware

stage 3 loads

u-boot-octeon_rhino_itus7x.bin

U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: May 04 2015 - 15:37:16)

two things here
1. the name of stage 3 files seemed to have been change from u-boot-octeon_sff7000.bin to u-boot-octeon_rhino_itus7x.bin

2. the build time for this file is now May 2015

the good new is that both these files can be copied to the Shield. The Shield seemed to have trouble loading either the stage 2 file or stage3 file from the memory. The only way to correct this is with a console cable  I prefer a usb console cable.

Here is my start up screen stop just after loading stage3


OCTEON eMMC stage 1 bootloader

Partition: 1, start: 0x0000000000000800, size: 0x0000000000200000
Reading 470976 bytes.
................................................................................................................... Done.
Loaded OCTBOOT2BIN, size: 0x0000000000072FC0
Branching to stage 2 at: 0xFFFFFFFF81004000
Board TLV descriptor Read - RHino continues ... 2 board 0x4e26 major 1 minor 0, DDR HERTZ 0 hz
Rhino: early board init, mem_clk 0x29b ..

U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: Mar 27 2015 - 10:49:38)

Initializing DRAM
U-Boot is not RAM-resident
Rhino: lookup_ddr_config_structure: cpu_id 890370 board_type 20006 ...
Rhino: cpu_id 0xd9602 board_type 0x4e26 major 0x1 minor 0x0  mask 1 ...
Initializing DDR, clock = 667000000hz, reference = 50000000hz
LMC0_DCLK_CNT: 0xffffffffffffffff
Measured DDR clock 666666654 Hz
Mem size in MBYTES: 1024
RHino: new Ram size 1024MiB (0x40000000)
Ram size 1024MiB (0x40000000)
Clearing memory from 0 to 1048576
Done clearing memory
CUST_PRIVATE_RHINO_ITUS7X board revision major:1, minor:0, serial #:
OCTEON CN7020-AAP pass 1.2, Core clock: 1000 MHz, IO clock: 600 MHz, DDR clock: 667 MHz (1334 Mhz DDR)
Base DRAM address used by u-boot: 0x4f804000, size: 0x7fc000
DRAM: 1 GiB
Clearing DRAM.....Clearing base address: 0x100000, size: 0xff00000, ub_base: 0x4f804000, ub_size: 0x7fc000
Stack: 0xc03f5c60
Done clearing memory, ub_base: 0x4f804000
.Clearing base address: 0x20000000, size: 0x30000000, ub_base: 0x4f804000, ub_size: 0x7fc000
Stack: 0xc03f5c60
Done clearing memory, ub_base: 0x4f804000
 done
Using default environment

MMC:   Octeon MMC/SD0: 1
Hit any key to stop autoboot:  0
reading u-boot-octeon_rhino_itus7x.bin
early_board_init: Early board init .................
Importing environment from RAM address 0x1000
RAM environment is 33 bytes

U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: May 04 2015 - 15:37:16)