Posted by
duanev on
Jan 28, 2017; 10:15pm
URL: https://itus.accessinnov.com/Current-state-of-Sheild-recovery-knowledge-tp1249p1349.html
Sorry, got side tracked there for a while :)
Ok, with no SD card, holding the reset button down (with a paperclip) before power on, and holding the reset down with the clip for 30 seconds after powering up the ITUS, seems to do nothing at all. The serial port output does not appear to recognize the reset, or wait for the reset button to be released, it just proceeds with the normal stage 1 and 2 boot ending at the Octeon sff7000# prompt.
samtec55@gmail.com wrote
Try this
1) make sure no sd card insert
2) factory restart via ping ( remove poewer hold ping in and then reconnect power continue to hold pin in for 30 seconds)
3) wait 10 minutes
4) can you log in ?
if you can't log in can you take screen shots of the boot process screen via the serial cable
Here is the captured output (with the ctrl characters embedded):
^M
OCTEON eMMC stage 1 bootloader^M
^M
Partition: 1, start: 0x0000000000000800, size: 0x0000000000200001^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
OCTBOOT2BAK not found^M
OCTBOOT2BIN not found^M
^M
Error: Trying embedded failsafe...^M
Success.^M
Branching to stage 2 at: 0xFFFFFFFF81004000^M
board_init_f: Done calling 4 (0xc00756b0)^M
Calling 5: 0xc002b3a8^M
board_init_f: Boot flag: 0x2^M
__octeon_setup_clocks: cpu: 1000000000, bus: 600000000^M
__octeon_setup_clocks: core: 1000000000, I/O: 600000000^M
board_init_f: Done calling 5 (0xc00756b4)^M
Calling 6: 0xc00413a8^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 6 (0xc00756b8)^M
Calling 7: 0xc002b294^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 7 (0xc00756bc)^M
Calling 8: 0xc002b58c^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 8 (0xc00756c0)^M
Calling 9: 0xc002f934^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 9 (0xc00756c4)^M
Calling 10: 0xc0053920^M
board_init_f: Boot flag: 0x2^M
Board TLV descriptor Read - RHino continues ... 2 board 0x40 major 1 minor 0, DDR HERTZ 0 hz^M
Rhino: early board init, mem_clk 0x29b ..^M
board_init_f: Done calling 10 (0xc00756c8)^M
Calling 11: 0xc0025978^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 11 (0xc00756cc)^M
Calling 12: 0xc0024cf0^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 12 (0xc00756d0)^M
Calling 13: 0xc002b32c^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 13 (0xc00756d4)^M
Calling 14: 0xc00473b8^M
board_init_f: Boot flag: 0x2^Mboard_init_f: Done calling 14 (0xc00756d8)^M
Calling 15: 0xc0037d90^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 15 (0xc00756dc)^M
Calling 16: 0xc002b2b0^M
board_init_f: Boot flag: 0x2^M
^M
^M
U-Boot 2013.07 (Development build, svnversion: u-boot:exported, exec:) (Build time: Dec 01 2014 - 16:34:53)^M
^M
board_init_f: Done calling 16 (0xc00756e0)^M
Calling 17: 0xc0022204^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 17 (0xc00756e4)^M
Calling 18: 0xc00237b8^M
board_init_f: Boot flag: 0x2^M
Initializing DRAM^M
U-Boot is not RAM-resident^M
Found DDR configuration for SFF7000^M
Rhino: cpu_id 0xd9602 board_type 0x40 major 0x1 minor 0x0 mask 1 ...^M
Initializing DDR, clock = 667000000hz, reference = 50000000hz^M
LMC0_DCLK_CNT: 0xffffffffffffffff^M
Cavium Inc. OCTEON SDK version 3.1.0_p4, build 534: $Revision: 101360 $^M
EARLY FILL COUNT : 13, cpu_hertz:1000000000, ddr_hertz:667000000^M
LMC0 Asserting DDR_RESET_L^M
DDR Reference Hertz = 50000000^M
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334^M
clkr: 0, en[2]: 3, clkf: 39, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334^M
clkr: 1, en[2]: 3, clkf: 79, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334^M
clkr: 2, en[2]: 3, clkf: 119, pll_MHz: 2000, ddr_hertz: 666666666, error: 333334^M
clkr: 2, en[1]: 2, clkf: 79, pll_MHz: 1333, ddr_hertz: 666666666, error: 333334^M
clkr: 0, en[5]: 6, clkf: 79, pll_MHz: 4000, ddr_hertz: 666666666, error: 333334 <==^M
LMC0 De-asserting DDR_RESET_L^M
LMC0: Measured DDR clock: 666666480, cpu clock: 1000000000, ddr clocks: 111111419^M
LMC0: measured speed: 666666480 hz^M
^M
Initializing DDR interface 0, DDR Clock 666666480, DDR Reference Clock 50000000, CPUID 0x000d9602^M
spd_addr : 0x0019^M
spd_org : 0x0002^M
row_lsb = column_bits_start + col_bits + bank_bits = 15^M
pbank_lsb = row_lsb + row_bits + bunk_enable = 30^M
row bits: 15, col bits: 10, banks: 8, ranks: 1, dram width: 16, size: 1024 MB^M
DRAM Interface width: 32 bits ^M
spd_cas_latency : 0x00fe^M
spd_twr : 0x0078^M
spd_trcd : 0x006e^M
spd_trrd : 0x0030^M
spd_trp : 0x006e^M
spd_tras : 0x0118^M
spd_trc : 0x0186^M
spd_trfc : 0x0820^M
spd_twtr : 0x003c^M
spd_trtp : 0x003c^M
spd_tfaw : 0x00f0^M
spd_addr_mirror : 0x0000^M
^M
------ Board Custom Configuration Settings ------^M
MIN_RTT_NOM_IDX : 1^M
MAX_RTT_NOM_IDX : 5^M
MIN_RODT_CTL : 1^M
MAX_RODT_CTL : 5^M
DQX_CTL : 4^M
CK_CTL : 4^M
CMD_CTL : 4^M
CONTROL_CTL : 4^M
MIN_CAS_LATENCY : 0^M
OFFSET_EN : 1^M
OFFSET_UDIMM : 2^M
OFFSET_RDIMM : 2^M
DDR_RTT_NOM_AUTO : 0^M
DDR_RODT_CTL_AUTO : 0^M
RLEVEL_COMP_OFFSET : 7^M
RLEVEL_COMPUTE : 0^M
DDR2T_UDIMM : 1^M
DDR2T_RDIMM : 1^M
FPRCH2 : 2^M
-------------------------------------------------^M
Desired CAS Latency : 10^M
CAS Latencies supported in DIMM : 5 6 7 8 9 10 11^M
CAS Latency : 10^M
DDR Clock Rate (tCLK) : 1500 ps^M
Core Clock Rate (eCLK) : 1000 ps^M
Medium Timebase (MTB) : 125 ps^M
Minimum Cycle Time (tCKmin) : 1250 ps^M
Minimum CAS Latency Time (tAAmin) : 13750 ps^M
Write Recovery Time (tWR) : 15000 ps^M
Minimum RAS to CAS delay (tRCD) : 13750 ps^M
Minimum Row Active to Row Active delay (tRRD) : 6000 ps^M
Minimum Row Precharge Delay (tRP) : 13750 ps^M
Minimum Active to Precharge (tRAS) : 35000 ps^M
Minimum Active to Active/Refresh Delay (tRC) : 48750 ps^M
Minimum Refresh Recovery Delay (tRFC) : 260000 ps^M
Internal write to read command delay (tWTR) : 7500 ps^M
Min Internal Rd to Precharge Cmd Delay (tRTP) : 7500 ps^M
Minimum Four Activate Window Delay (tFAW) : 30000 ps^M
LMC_SCRAMBLE_CFG0 : 0x0000000000000000^M
LMC_SCRAMBLE_CFG1 : 0x0000000000000000^M
LMC_CONFIG : 0x1008090a2c290044^M
LMC_CONTROL : 0x000007801f038024^M
TIMING_PARAMS0 : 0x000065112ccc3400^M
TIMING_PARAMS1 : 0x0000f2bd34592970^M
CAS Write Latency : 7^M
Write recovery for auto precharge (WRP) : 5^M
MODEREG_PARAMS0 : 0x0000000000a30002^M
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3^M
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0^M
DIC 40, 40, 40, 40 ohms : 0,0,0,0^M
MODEREG_PARAMS1 : 0x0000000000000600^M
LMC_NXM : 0x000000000000040e^M
WODT_MASK : 0x0000000000000001^M
RODT_MASK : 0x0000000000000000^M
DYN_RTT_NOM_MASK : 0x00^M
PHY_CTL : 0x0000001200000000^M
PHY_CTL : 0x0000001200200000^M
Performing Write-Leveling^M
MODE32B : 1^M
Rank(0) Wlevel Debug Results : 00000 00000 00000 00000 00000 0001e 0001f 000f0 000f8^M
Rank(0) Wlevel Rank 0x3, 0x0000600000000082 : 0 0 0 0 0 0 0 4 2^M
MODE32B : 1^M
Waiting 159448 usecs for ZQCS calibrations to start^M
Performing Read-Leveling^M
RLEVEL_CTL : 0x00000000553c3f20^M
RLEVEL_OFFSET : 2^M
RLEVEL_OFFSET_EN : 1^M
DDR__PTUNE/DDR__NTUNE : 8/7^M
^M
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3^M
Read ODT_CTL : 0x5 (120 ohms)^M
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 00ffe 00fff 001f0 001f0^M
Rank(0) Rlevel Rank 0x3, 0x00C6186186249186 : 6 6 6 6 6 9 9 6 6 (57)^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=5][rankx=0].score:57^M
Read ODT_CTL : 0x4 (60 ohms)^M
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 000fe 000ff 001f0 001f0^M
Rank(0) Rlevel Rank 0x3, 0x00C6186186145186 : 6 6 6 6 6 5 5 6 6 (15)^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=4][rankx=0].score:15^M
Read ODT_CTL : 0x3 (40 ohms)^M
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 000fe 000f7 001f0 001f0^M
Rank(0) Rlevel Rank 0x3, 0x00C6186186145186 : 6 6 6 6 6 5 5 6 6 (9)^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=3][rankx=0].score:9^M
Read ODT_CTL : 0x2 (30 ohms)^M
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 000fe 000f7 001f0 001f0^M
Rank(0) Rlevel Rank 0x3, 0x00C6186186145186 : 6 6 6 6 6 5 5 6 6 (9)^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=2][rankx=0].score:9^M
Read ODT_CTL : 0x1 (20 ohms)^M
Rank(0) Rlevel Debug Test Results 8:0 : 00000 00000 00000 00000 00000 00000 000f6 00000 001f0^M
Rank(0) Rlevel Rank 0x3, 0x00C6186186005006 : 6 6 6 6 6 0 5 0 6 (234)^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=1][rankx=0].score:234^M
DDR__PTUNE/DDR__NTUNE : 8/7^M
Evaluating Read-Leveling Scoreboard.^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=5][rankx=0].score:57^M
rodt_score:57, best_rodt_score:9999999^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=4][rankx=0].score:15^M
rodt_score:15, best_rodt_score:57^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=3][rankx=0].score:9^M
rodt_score:9, best_rodt_score:15^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=2][rankx=0].score:9^M
rodt_score:9, best_rodt_score:9^M
rlevel_scoreboard[rtt_nom=2][rodt_ctl=1][rankx=0].score:234^M
rodt_score:234, best_rodt_score:9^M
RTT_NOM 0, 0, 0, 40 ohms : 0,0,0,3^M
RTT_WR 0, 0, 0, 0 ohms : 0,0,0,0^M
DIC 40, 40, 40, 40 ohms : 0,0,0,0^M
Read ODT_CTL : 0x3 (40 ohms)^M
Rank(0) Rlevel Rank 0x1, 0x0046186186145186 : 6 6 6 6 6 5 5 6 6 (9)^M
DDR2T : 1^M
Performing software Write-Leveling^M
Rank Address: 0x0^M
Testing byte 0 delay 2^M
1: [0x8000000004000000] 0x00000000000000BF expected 0x00000000000000FF xor 0000000000000040^M
byte 0 delay 2 Errors^M
Testing byte 0 delay 10^M
byte 0(0x0) delay 10 Passed^M
Testing byte 1 delay 4^M
1: [0x8000000004000000] 0x000000000000BF00 expected 0x000000000000FF00 xor 0000000000004000^M
byte 1 delay 4 Errors^M
Testing byte 1 delay 12^M
byte 1(0x0) delay 12 Passed^M
Testing byte 2 delay 0^M
1: [0x8000000004000000] 0x0000000000BF0000 expected 0x0000000000FF0000 xor 0000000000400000^M
byte 2 delay 0 Errors^M
Testing byte 2 delay 8^M
byte 2(0x0) delay 8 Passed^M
Testing byte 3 delay 0^M
1: [0x8000000004000000] 0x00000000BF000000 expected 0x00000000FF000000 xor 0000000040000000^M
byte 3 delay 0 Errors^M
Testing byte 3 delay 8^M
byte 3(0x0) delay 8 Passed^M
Rank(0) Wlevel Rank 0x1, 0x0000200000A4218A : 0(e) 0(e) 0(e) 0(e) 10(e) 8 8 12 10 ^M
LMC0 Configuration Completed: 1024 MB^M
Measured DDR clock 666666480 Hz^M
Mem size in MBYTES: 1024^M
RHino: new Ram size 1024MiB (0x40000000)^M
Ram size 1024MiB (0x40000000)^M
Clearing memory from 0 to 1048576^M
Done clearing memory^M
board_init_f: Done calling 18 (0xc00756e8)^M
Calling 19: 0xc002b2f0^M
board_init_f: Boot flag: 0x2^M
Empty memory test^M
board_init_f: Done calling 19 (0xc00756ec)^M
Calling 20: 0xc0025a18^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 20 (0xc00756f0)^M
Calling 21: 0xc0053918^M
board_init_f: Boot flag: 0x2^M
board_init_f: Done calling 21 (0xc00756f4)^M
Calling 22: 0xc002ed50^M
board_init_f: Boot flag: 0x2^M
SFF7000 board revision major:1, minor:0, serial #: ^M
OCTEON CN7020-AAP pass 1.2, Core clock: 1000 MHz, IO clock: 600 MHz, DDR clock: 667 MHz (1334 Mhz DDR)^M
Rhino: End of display banner ...^M
board_init_f: Done calling 22 (0xc00756f8)^M
board_init_f: Done calling init sequence^M
flushing L2 cache...^M
Invalidating icache^M
Done.^M
Unlocking U-Boot from cache...^M
^M
Done.^M
RHino: relocation to DRAM ... RAM_SIZE 40000000^M
Rhino: N63XX and newer addr 0x50000000 offset 0x30000000 ...^M
U-Boot link addr: 0xc0004000^M
Top of RAM usable for U-Boot at: 50000000^M
Using TLB mapping size of 0x400000 bytes for DRAM mapping.^M
Reserving 1920k for U-Boot at: 4f804000^M
Clearing 0x7fc000 bytes at addr 0x4f804000^M
u_boot_base_phys: 0x4f804000, len: 0x1e0000^M
Reserving 2056k for malloc() at: 4f9e4000^M
Stack top physical address: 0x4fc16000^M
Reserving 80 bytes for Board Info at: 0x4fc15fb0^M
Reserving 320 Bytes for Global Data at: 0x4fc15e70^M
Reserving 128k for boot params() at: 4fbf5e70^M
Stack Pointer at: 4fbf5e60, stack size: 0x00030000^M
Base DRAM address used by u-boot: 0x4f804000, size: 0x7fc000^M
DRAM: 1 GiB^M
Top of fixed address reserved memory: 0x0006c188^M
gd address: ffff9910, new_addr: 0x4fc15e70^M
Relocating bd from: ffff9a50 to 0x800000004fc15fb0, size: 0x50^M
Relocating gd from: ffff9910 to 0x800000004fc15e70, size: 0x140^M
relocating and jumping to code in DRAM at addr: 0x4f804000^M
Virtual stack top: 0xc03f5e60, virt new gd: 0xc0415e70^M
Now running in RAM - U-Boot at: ffffffffc0004000^M
Relocation offset: 0x0, monitor base: 0xc0004000^M
U-Boot memory end: c01d8200^M
Setting heap memory to start at 0xc01e0000, size: 0x202000^M
Adding map entry for 0xc0004000, address: 0x4f804000, size: 0x400000, index: 0^M
About to flush L2 cache^M
ram size: 0x40000000 (1073741824), sizeof=8^M
Clearing DRAM.....Clearing base address: 0x100000, size: 0xff00000, ub_base: 0x4f804000, ub_size: 0x7fc000^M
Stack: 0xc03f5c60^M
Done clearing memory, ub_base: 0x4f804000^M
.Clearing base address: 0x20000000, size: 0x30000000, ub_base: 0x4f804000, ub_size: 0x7fc000^M
Stack: 0xc03f5c60^M
Done clearing memory, ub_base: 0x4f804000^M
done^M
Clearing DRAM ECC errors^M
Initializing phy mem list: ram_size: 0x40000000, low reserved size: 0x80000^M
Bootloader boot memory descriptor at 8006c108^M
Allocating named block for used memory.^M
Copying FDT from 0xc0054c70 to 0x80000, 3630 bytes^M
Increase FDT size to 0x20000^M
Performing board FDT fixups^M
BOOTLOADER_BOOTMEM_DESC_ADDR: 0x6c100^M
BOOTLOADER_BOOTMEM_DESC_SPACE: 0x6c108^M
size of bootmem desc: 56, location: 8006c108^M
Setting up simple executive support^M
Enabling all cores^M
octeon_enable_all_cores^M
Powering up cores on node 0^M
Relocating environment^M
Using default environment^M
^M
Environment relocated^M
Allocating idle core named block^M
Linux reserved load size 0x10000000^M
Adjusted memory top is 0x40000000^M
Setting load address to 0x20000000, size 0x10000000^M
Reserving 0xf000000 bytes of memory at 0x100000 for the Linux kernel^M
bootmem descriptor address (looked up): 0x6c108^M
Setting up U-Boot prompt for board type 64.^M
prompt environment variable not set.^M
Setting prompt to Octeon sff7000# ^M
Reading eeprom...^M
Performing OCTEON FDT fixups^M
Packing flat device tree^M
Setting numcores to 2^M
ethaddr not found in environment^M
Setting IP address...^M
Done.^M
Reserving first 1MB of memory^M
Initializing stdio...^M
Initializing jump table...^M
Initializing console...^M
Console initialized^M
Setting stdin, stdout and stderr to serial port^M
Setting load address...^M
Configuring misc...^M
MMC: Octeon MMC/SD0: 1^M
Doing late board init...^M
Setting serial number to ^M
Entering main loop.^M
Hit any key to stop autoboot: 3 ^H^H^H 2 ^H^H^H 1 ^H^H^H 0 ^M
reading u-boot-octeon_sff7000.bin^M
Could not read u-boot-octeon_sff7000.bin, trying failsafe^M
Error: environment variable octeon_stage3_failsafe_bootloader is not set.^M
Octeon sff7000#